发明名称 SYNCHRONIZING LOGIC AVOIDING METASTABILITY
摘要 According to the invention an apparatus is provided comprising a first circuit with a first clock signal (CLOCK1) at a first clock rate and a second circuit with a second clock signal (CLOCK2) at a second clock rate, the second circuit comprising an input circuit coupled to the first circuit and receiving signals therefrom. The apparatus further comprises a control circuit for controlling possible metastability situations in a communication between the first circuit and the second circuit. The control circuit receives as input the first clock signal and the second clock signal and comprises means for providing a shifting of at least one of the both clock signals, or parts thereof, in such a way that a possible metastable state of the input circuit is avoidable. A possible metastability situation in an apparatus according to the invention is controlled by monitoring the first clock signal and the second clock signal. When a possible metastability situation has been detected, at least one of the both clock signals, or parts thereof, is shifted, preferably advanced or delayed, in such a way that a possible metastable state of the input circuit can be avoided.
申请公布号 WO9706491(A1) 申请公布日期 1997.02.20
申请号 WO1995EP03170 申请日期 1995.08.10
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION;GOLDRIAN, GOTTFRIED 发明人 GOLDRIAN, GOTTFRIED
分类号 G06F13/42;H04L7/00;H04L7/033;(IPC1-7):G06F13/42 主分类号 G06F13/42
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