发明名称 |
PHASE LOCKED LOOP CIRCUIT |
摘要 |
PROBLEM TO BE SOLVED: To prevent the malfunction of the circuit caused by the interruption of a reference clock by providing a missing clock detection circuit to a PLL circuit using a phase comparator circuit. SOLUTION: A missing clock detection circuit 5 is provided with an input terminal RIN for a reference clock Rin and an input terminal DIN for a detection clock DETTCK whose speed is higher than the reference clock Rin. A phase comparator 1 is so configured that it restores to an initial state when an output signal S5 of the missing clock detection circuit 5 is given to a reset terminal DRST and lead information S1u goes to an L level and delay information S1d goes to an H level. When a missing clock takes place in the reference clock Rin, the missing clock detection circuit 5 outputs an L level output signal S to reset the phase comparator 1, which is restored to the initial state. When the phase comparator 1 restores to the initial state to set the lead information S1u to an L level and the delay information S1d to an H level so as to prevent malfunction of the phase comparator caused by a missing clock thereby realizing a stable operation. |
申请公布号 |
JPH0951267(A) |
申请公布日期 |
1997.02.18 |
申请号 |
JP19950202180 |
申请日期 |
1995.08.08 |
申请人 |
OKI ELECTRIC IND CO LTD;NIPPON TELEGR & TELEPH CORP <NTT> |
发明人 |
TAKAHASHI AKIHIRO;KAKINUMA RIYUUMA |
分类号 |
H03L7/14 |
主分类号 |
H03L7/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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