Method and apparatus for a low power self-timed memory control system

摘要

A self-timed memory control system including a dummy row and column of memory cells along adjacent edges of a core memory array. Control logic receives an external clock signal and initiates address decoding, and also asserts a sense enable signal for activating the sense amplifiers. A dummy driver receives the enable signal and asserts a select signal on a dummy select line, which causes a memory access to occur in the dummy portion simultaneously with each access of the core memory array. A fixed memory cell in the dummy path always asserts a logic zero to a dummy sense amplifier, which senses the logic zero and respondingly asserts a timing signal. The dummy sense amplifier is biased with a voltage offset to favor a logic one, so that the timing signal is preferably delayed until after the output data of the core memory array has stabilized. The control logic detects the assertion of the timing signal and respondingly latches the output data, and the control logic also shuts down the sense amplifiers to prevent further power drain. In this manner, the output data is latched and the sense amplifiers are disabled as soon as possible to conserve energy but within a safe timing margin to assure that valid data is properly latched. A biased inverter is preferably added for further timing margin. The sense amplifiers preferably include an input level-shifter stage for proper operation at low voltage levels.