发明名称 Fabrication process for an interconnection substrate allowing to connect a die to a carrier substrate
摘要 To develop an interconnecting substrate, to link at least one microchip on a reception substrate, a layer of fusible material (102) is laid on a substrate (100). An initial layer (104) of dielectric material is etched to allow the openings (106) to match the outlet terminals of the interconnecting substrate. Metal pads (108) are formed in the openings (106) to give the outlet terminals, to be covered by a metal layer (110). The metal layer (110) is etched to give the conductive paths (112), overlapping the openings (106) in the dielectric material (104), at least partially, under the metal layer (110). A layer of dielectric material (114) is over the conductive paths, and is etched to give openings at least partially over the conductive paths (112), to be filled with metal pads. The interconnecting substrate is separated by heat, at a temp. equal to or greater than the melting temp. of the fusible layer (102). The dielectric material is of pref. of polyimide.
申请公布号 EP0751556(A1) 申请公布日期 1997.01.02
申请号 EP19960401425 申请日期 1996.06.27
申请人 COMMISSARIAT A L'ENERGIE ATOMIQUE 发明人 CAILLAT, PATRICE;HENRY, DAVID
分类号 H05K1/18;H01L21/48;H01L21/68;H01L23/32;H05K1/14;H05K3/36 主分类号 H05K1/18
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