发明名称 |
Semiconductor integrated circuit device |
摘要 |
Read signals to be outputted in the unit of bits from a packaged RAM are received to produce complementary output signals, and these output signals and the non-inverted and inverted signals of expected values are individually inputted to two logic circuits, so that the outputs of the logic circuits are compared by a coincidence/incoincidence circuit to produce a decision output.
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申请公布号 |
US5583817(A) |
申请公布日期 |
1996.12.10 |
申请号 |
US19950382592 |
申请日期 |
1995.02.02 |
申请人 |
HITACHI, LTD. |
发明人 |
KAWAGUCHI, ETSUKO;HIGETA, KEIICHI;FUJIMURA, YASUHIRO;YAMAGUCHI, KUNIHIKO |
分类号 |
G11C7/10;G11C29/36;(IPC1-7):H01L27/10 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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