发明名称 |
PREPARATION OF MOS INTEGRATED CIRCUIT HAVING PART WITH DIFFERENT INSULATING MATERIAL |
摘要 |
PROBLEM TO BE SOLVED: To intrinsically improve a resistance with respect to the degradation of an oxide caused by electric charges passing through a cell oxide during a memory operation, when a thin thermal oxide is formed in a memory cell and in the region of the parts of the other periphery circuit of the memory. SOLUTION: An oxide is nitrided at high temperature. As a modification, a nitrided oxide formed in the region which is formed for manufacturing parts of a peripheral circuit is removed, then a similar thermal oxidation treatment is performed, for a later high-temperature nitriding. |
申请公布号 |
JPH08306809(A) |
申请公布日期 |
1996.11.22 |
申请号 |
JP19960054682 |
申请日期 |
1996.03.12 |
申请人 |
SGS THOMSON MICROELETTRONICA SPA |
发明人 |
GABURIEERA GIDEINI;CHIEZARE KUREMENTEI |
分类号 |
H01L21/314;H01L21/8239;H01L21/8242;H01L21/8247;H01L27/105;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L21/824 |
主分类号 |
H01L21/314 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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