发明名称 |
PICTURE SIGNAL PROCESSOR |
摘要 |
Interlace scan PALplus signals are fed to a 133-line delay (32) which is a delay element of 133 lines. The output of the delay element is fed to field memories (23 and 25). The memory (23) is a first memory for one-field delay and the output of the memory (23) is fed to a field memory (24) which is provided as a second memory. The memory (24) performs shuffling on a field A and, at the same time, data in the memory (24) is read at a double speed so that the same field A may appear continuously four times. The field memory (25) which is provided as a third memory is controlled so that readout from the memory (25) may be started prescribed time after write and performs shuffling on a field B. At the same time, readout from the memory (25) is performed at a double speed so that the same field B may appear continuously four times. The picture signals read out from the memories (24 and 25) are fed to a vertical filter/median processing section (26) which is provided as a scanning line interpolating means.
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申请公布号 |
WO9631054(A1) |
申请公布日期 |
1996.10.03 |
申请号 |
WO1996JP00822 |
申请日期 |
1996.03.28 |
申请人 |
SONY CORPORATION |
发明人 |
TATEHIRA, YASUSHI;KANOU, MAMORU;KITA, HIROYUKI |
分类号 |
H04N7/00;H04N7/01;H04N7/015;H04N11/16;H04N11/18;(IPC1-7):H04N7/015 |
主分类号 |
H04N7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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