| 摘要 |
<p>A block write function is added to a synchronous dynamic RAM, and a unit decoder circuit is used for its column decoder. This unit decoder circuit includes a plurality of CMOS inverter circuits for receiving a plurality of first pre-decode signals and forming column select signals, and a CMOS circuit for receiving one of a plurality of second pre-decode signals and supplying its output signals to the common source of N-channel MOSFETs in the CMOS inverter circuits described above. The second pre-decode signal is generated by using lower order address signals. Therefore, only a P-channel MOSFET and an N-channel MOSFET are connected to the address line which is simultaneously changed at the time of block write, and power consumption can be reduced. Since one decoder of each unit forms the select signal, the current flowing through the CMOS inverter circuits can be dispersed to the MOSFETs receiving the second pre-decode signal. Therefore, it is not necessary to enlarge the size of such MOSFETs for the block write operation, and high integration becomes possible.</p> |
