发明名称 Timing model and characterization system for logic simulation of integrated circuits
摘要 A method approximates propagation delay through a logic device. Operation of the logic device is divided into a first region and a second region. A boundary between the first region and the second is based on duration of input ramp to the logic device and amount of capacitive load driven by the logic device. For example, the boundary between the first region and the second occurs where for each value of the capacitive load, an output ramp for the logic device is one half complete when the input ramp is complete. When the logic device operates in the first region, a first formula is used to obtain a first value representing delay through the logic device. The first formula varies the first value based on the duration of the input ramp to the logic device and the capacitive load driven by the logic device. When the logic device operates in the second region, a second formula is used to obtain the first value. The second formula also varies the first value based on the duration of the input ramp to the logic device and the capacitive load driven by the logic device.
申请公布号 US5548526(A) 申请公布日期 1996.08.20
申请号 US19920849242 申请日期 1992.03.11
申请人 VLSI TECHNOLOGY, INC. 发明人 MISHELOFF, MICHAEL N.
分类号 G06F17/50;(IPC1-7):G06F17/10;G06F17/17 主分类号 G06F17/50
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