发明名称 |
Interface and control circuit for regulating data flow in a SCSI initiator with multiple host bus interface selection |
摘要 |
A single chip SCSI controller circuit has a pair of input and output first in, first out (FIFO) buffers as well as a main buffer. The circuit supports synchronous and asynchronous data transfers which are fully compatible with the SCSI-II specification. A mode select pin may be selectively actuated by the user or by attached interface circuitry to configure the chip for either microchannel architecture (MCA) or industry standard architecture (ISA) compatibility.
|
申请公布号 |
US5544326(A) |
申请公布日期 |
1996.08.06 |
申请号 |
US19930029910 |
申请日期 |
1993.03.11 |
申请人 |
FUTURE DOMAIN CORPORATION, INCORPORATED |
发明人 |
PEASE, ALLAN F.;MOORE, RICHARD |
分类号 |
G06F5/10;G06F5/12;G06F13/12;G06F13/40;(IPC1-7):G06F13/38 |
主分类号 |
G06F5/10 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|