VITERBI DECODER IN CODE DIVISION MULTIPLE ACCESS

摘要

a control signal generator for generating control signals(wen,c0,c1,c2,c3) for controlling selective reading of the data block stored in a memory; a count signal generator for generating count signals(ad.0-ad.8) in a predetermined bit; a decoder for decoding the count signals to generate m-bit addresses to/from which data is inputted/outputted; and an address selector for combining the m-bit addresses by 8-bit unit and selectively outputting the bits included in each unit.