发明名称 |
Digital computer system having an improved direct-mapped cache controller (with flag modification) for a CPU with address pipelining and method therefor |
摘要 |
A digital computer system having a "smart" cache controller that permits the system to take advantage of CPU address pipelining while minimizing the performance impact of a pipelined cache read miss in a system with a relatively low hit ratio such as a direct mapped cache.
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申请公布号 |
US5535360(A) |
申请公布日期 |
1996.07.09 |
申请号 |
US19940298989 |
申请日期 |
1994.08.31 |
申请人 |
VLSI TECHNOLOGY, INC. |
发明人 |
CASSETTI, DAVID K. |
分类号 |
G06F12/08;(IPC1-7):G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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