FIFO memory management device

摘要

The FIFO memory manager has a read control port and a write control port, activated respectively by a read and write command signal. The different possible access states are computed and stored, and a 'current access state' is selected and delivered as a current state message. The access state computation and storage circuit has a first access increment port, with an adder and a bistable flip-flop memory used by a write signal. A second access port with a subtractor is associated with a read operation. A third access port for simultaneous read and write operations maintains the state. A multiplexer circuit receives signals from the three access ports, and has a selector input to determine which port is used.