| 摘要 |
PURPOSE: To prevent step discontinuity or bridging of an upper layer wiring layer by improving surface flatness by relieving difference in level acompanying a multilayer silicon structure simultaneously with improving an integration degree by forming a high resistance element of a non-doped polycrystalline layer. CONSTITUTION: In a semiconductor device 30, a non-doped second polycrystalline silicon layer 40 of the uppermost layer is used entirely with no patterning as a high-resistance element as it is. Further, a first aluminium wiring layer 43 formed on the high resistance element is connected to a source region 33 through a contact hole 45 passing through a second polycrystalline silicon layer 40. Further, an insulating layer 46 is interposed between a second polycrystalline silicon layer 40 and a first aluminium wiring layer 43 by oxidizing an exposed end part inside a contact hole 45 of a second polycrystalline silicon layer 40 so as to attain electric insulation between both of them. |
