| 摘要 |
<p>PURPOSE: To improve a defect detection rate even when difference between preceding and following digital values to be digital/analog (D/A) converted is less than allowable error by generating data to be a value to exceed the allowable error to which the interval of input data is set. CONSTITUTION: A CPU 3 sets a first converting value FFH to a D/A converting value setting register 8 and a D/A converting part 7 starts conversion. A generated analog voltage is inputted to an external A/D converter 15 and its output is stored in a memory 4. Then, a decision upper limit value is generated by summing the value of the register 8 and allowable error NH, and compared with the converted result. When the decision shows OK, a carry flag CY is turned to '0' and when the CY is '1', the decision is turned to NG. Similarly, a decision lower limit value is generated and decided. The converting digital value is set to the register 8 again, and the converted FFH and 80H are ANDed. When no CY rises, the FFH and FFH are exclusively ORed and a provided 00H becomes the next converting digital value. The 00H and 80H are ANDed again and the FFH is decremented and defined as the next converting digital value.</p> |
