发明名称 DEAD TIME COMPENSATION CIRCUIT
摘要 PURPOSE: To provide a dead time compensation circuit which detects the failure of a voltage detection circuit for detecting the state of the output voltage of a main circuit to be supplied to a load and at the same time transmits an output signal by switching from a dead time compensation output signal to a PWM command when the failure is detected. CONSTITUTION: A specific counting operation is made by a counter A12 while a PWM command U* and a dead time compensation output signal U' differ by obtaining the exclusive OR between the PWM command U* and the dead time compensation output signal U', an SR latch circuit A13 is set by detecting the failure of a voltage detection circuit due to the generation of the overflow signal of the counter A12, and at the same time a selection switch A14 is switched for changing from the dead time compensation output U' to the PWM command U*, thus outputting the PWM command U*.
申请公布号 JPH08140362(A) 申请公布日期 1996.05.31
申请号 JP19940276193 申请日期 1994.11.10
申请人 MEIDENSHA CORP 发明人 YAMAMOTO YASUHIRO
分类号 H02M1/00;H02M7/48;H02M7/537 主分类号 H02M1/00
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