Tileable gate array cell for programmable logic devices and gate array having tiled gate array cells

摘要

A logic and routing cell for constructing a programmable gate array. The gate array may be constructed by tiling a wafer surface with this single logic and routing cell design. The logic and routing cell includes both the logic cell and the routing circuitry needed to connect that logic cell to all levels of a hierarchical routing system for making connections between the various logic cells.