| 摘要 |
PURPOSE: To obtain the delay adjustment device without being affected by fading or the like after the end of setting operation of delay by progressing automatically a delay setting operation at a high speed. CONSTITUTION: A phase difference detection circuit 3, a center phase discrimination means 4 and a delay direction discrimination circuit 5 in each active system (n) compare a phase of a frame synchronizing signal obtained from an active system and a phase of a frame synchronizing signal from a standby system. A delay selection circuit 6 provides an output of a signal representing m-bit or 1-bit based on a phase difference of the two frame synchronizing signals. A delay arithmetic circuit 7 adds or subtracts a delay of the delay selection circuit 6 to/from a stored initial delay according to the delay direction. A delay storage circuit 8 stores the result of arithmetic operation by the delay arithmetic circuit 7. A control signal selection circuit 9 gives the result of arithmetic operation by the delay arithmetic circuit 7 to an arithmetic adjustment circuit 1 till the phases of two frame synchronizing signals are coincident and the result of arithmetic operation stored in the delay storage circuit 8 after the phases of two frame synchronizing signals are coincident to the arithmetic adjustment circuit 1. |
