Method for testing a test architecture within a circuit

摘要

A method for testing a test architecture in a circuit is accomplished by receiving or generating, based on the topology information for the circuit, a Boundary Scan Description Language (BSDL) description of the test architecture which is then verified for correct syntax, consistency, and standard compliance. Next, one or more tests are selected from a predetermined set of test methodologies, based on the type of testing to be performed. Self-checking test parameters are generated based on the BSDL description and the selected tests. Using these test parameters, a logic simulation algorithm tests the test architecture of the circuit and generates a report detailing any errors that are discovered.