| 摘要 |
PURPOSE: To attain control with an excellent band limiting characteristic by providing an AND logic gate, a period counter, a serial-parallel converter, a band limit filter ROM and an adder providing an output of wave whose frequency band is limited to the control circuit. CONSTITUTION: When a carrier control signal is logical 1, symbol data pass through an AND logic gate 11 and are given to a serial-parallel converter 14 without any modification. The converter 14 latches and shifts output data of the gate 11 synchronously with symbol clocks obtained by applying 1/k frequency division to the sample clock to provide an output of parallel data. A band limit filter ROM 16 receives a sample valve outputted by a period counter 13 and parallel data from the converter as addresses and outputs data to be uniquely decided. In this case, the counter 13 outputs a band limit signal obtained by applying K-multiple oversampling to a symbol period from the ROM 16 synchronously with the sample clock to secure the band limiting characteristic at signal transmission. |
