| 摘要 |
A family of CFET logic circuits (100, 200, 202 and 360) useful for wave-pipeline systems is described, and a method to design same. The invention uses complementary transmission logic gates (221, 222; 121, 122; and 321, 322, 323, 324) and pull-up (224) or pull-down transistors to achieve a family of CFET logic circuits which include AND, NAND, OR, NOR, XOR, XNOR, select, select-invert, and not-invert functions. Each circuit (100, 200, 202 and 360) is tuned to provide substantially equal delays, high-quality ones and zeros, and substantially equal rise and fall times, for every combination of input-state transition and output-state transition.
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