| 摘要 |
PURPOSE: To deal with the decode and display of input encoded data equipped with different frame frequencies by defining a clock frequency, which can generate regular horizontal synchronizing signal (hSync) and vertical synchronizing signal (vSync), as a display system clock concerning modes for two kinds of frame frequencies. CONSTITUTION: A timing unit 18 for supplying a clock signal and various kinds of processing timing to respective blocks inside the decoder of a buffer memory 11 or the like generates a display frame frequency matched with the frame frequency of input image data by frequency-dividing one display clock signal at a frequency dividing ratio corresponding to the frame frequency of input image data. In this case, first of all, the clock frequency to generate the regular hSync and vSync is adopted as the display clock concerning the modes for two kinds of frame frequencies. Therefore, when the frame frequency designated by the input encoded data is included in those two kinds of modes, data are outputted at a regular frequency. |
