| 摘要 |
<p>PURPOSE:To switch a system clock at high speed by forming an oscillating pulse by multiplying the pulse of a low frequency while using a PLL circuit, and outputting the clock corresponding to a low-speed/high-speed mode and the stability degree of a circuit. CONSTITUTION:At a clock pulse generating circuit built in the microprocessor, an oscillation circuit XOSC forms the oscillating pulse of the comparatively low frequency corresponding to the low-speed operating mode and the PLL circuit multiplies this pulse as a reference frequency signal so that two kinds of clock pulses DV1 and DV2 for the high-speed operating mode can be formed. When the microprocessor is set in the low-speed operating mode, clock pulses CK1 and CK2 of the comparatively low frequency are outputted and when any event requiring a high-speed operation is generated, multiplexers MUX 3 and MUX 4 continuously output the clock pulses for low speed until the PLL circuit is turned to an operating state and stabilized but when the PLL circuit is stabilized, clock pulses for a high-speed operation are outputted.</p> |
