| 摘要 |
A memory system including a memory array having at least two pairs of data lines, first and second data lines, that correspond to columns in the memory array. A first stage is included having inputs connected to the two pairs of data lines. The first stage also has a pair of output lines, a true output lines and a complement output line, wherein output signals generated in the output lines are controlled by a first and second set of transistors. Each transistor in the first set has a gate connected to one of the input lines, and each transistor in the second set is connected in series with one of the transistors in the first set and may be selectively turned on and turned off, wherein of one of the two pairs of data lines may be selected by turning transistors on and off in the second set.
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