发明名称 CMOS LOGIC CIRCUIT
摘要 <p>PURPOSE:To fix the delay time of a circuit against any temperature change or element dispersion. CONSTITUTION:Delay circuits 4 and 5 are constituted by serially connecting inverters while suitably selecting several stages, and time difference is generated in an input signal to a logic circuit (AND) circuit 6. The logic circuit 6 expresses that time difference as the ratio of applying time of one and another power supply voltages of the inverter and outputs it as an analog voltage value by using an integrator 7. A voltage comparator 8 compares the output voltage of the integrator 7 with a reference voltage 9. Based on that result, a voltage control means 10 generates the respective back gate voltages of P type and N type MOS transistors 13 and 14, controls respective threshold voltages and fixes transistor ability. When the delay time per inverter stage is changed corresponding to the threshold voltage, it is fed back and these operations are repeated until the output voltage is equal with the reference voltage 9. As a result, the initially set delay time is settled down, and the dispersion of delay time caused by any dispersion or the like is suppressed.</p>
申请公布号 JPH0823271(A) 申请公布日期 1996.01.23
申请号 JP19940157376 申请日期 1994.07.08
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HIDAKA IKUO
分类号 H03K19/003;G06F1/04;H03K19/0948;(IPC1-7):H03K19/003;H03K19/094 主分类号 H03K19/003
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