发明名称 |
High-speed staged decoder/quantizer |
摘要 |
A symbol-level pipelined structure for parallel systolic decoding of block codes which is a layered processor structure including a number of layers equal to the code length and each layer is adapted to decode the component codes of a concatenated code in sequence. The structure described provides efficient high rate decoding operation with an associated low cost and low hardware complexity.
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申请公布号 |
US5487075(A) |
申请公布日期 |
1996.01.23 |
申请号 |
US19940246516 |
申请日期 |
1994.05.20 |
申请人 |
AGENCE SPATIALE EUROPEENNE |
发明人 |
CAIRE, GUISEPPE;VENTURA TRAVESET, JAVIER;HOLLREISER, MARTIN;BIGLIERI, EZIO |
分类号 |
H03M13/05;H03M13/41;(IPC1-7):G06F11/10;H03M13/00 |
主分类号 |
H03M13/05 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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