A SPECIFIC BIT TRANSMISSION CIRCUIT

摘要

The circuit comprises a frame forming circuit for forming a signal as a serial bit stream of a kind of highway like 256 bits, or 2048bps; a FIFO circuit for regulating a timing for an input or an output of a read clock in order to write an output of the frame forming circuit according to a clock of a FIFO input clock terminal, and to read a written value from every fifth bit of each time slot of a T1 frame by means of a clock of a FIFO output clock terminal; and a T1 line interface circuit for transmitting the output signal of the FIFO circuit to a T1 line of 1.544Mbps.