发明名称 Method for planarizing an integrated circuit topography.
摘要 <p>A method is provided for forming a planarization structure of dielectric materials upon a substrate topography. The dielectric materials can be deposited in layers without removing one or more layers in non-contact areas prior to deposition of an overlying interconnect conductors. Alternatively, at least one layer can be entirely removed from the dielectric materials prior to deposition of the overlying interconnect conductors. A plasma oxide is placed between the substrate upper surface and a subsequently deposited TEOS oxide to reduce stress properties and to balance the stress between the TEOS oxide and the plasma oxide. A subsequently placed SOG layer can be used to further planarize the upper surface, wherein a capping layer is deposited above the SOG to prevent or substantially minimize water absorption. The SOG layer can, alternatively, be removed in its entirety in an etch-back procedure prior to capping layer deposition. Removal of the SOG layer prevents outgassing of water during times in which contacts are formed.</p>
申请公布号 EP0678914(A2) 申请公布日期 1995.10.25
申请号 EP19950301415 申请日期 1995.03.06
申请人 ADVANCED MICRO DEVICES INC. 发明人 DAWSON, ROBERT
分类号 H01L21/31;H01L21/3105;H01L21/316;H01L21/318;H01L21/3205;H01L21/768;H01L23/522;(IPC1-7):H01L21/768;H01L21/310 主分类号 H01L21/31
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