| 摘要 |
PURPOSE:To suppress frequency fluctuation in an output clock signal and phase/ frequency jump by providing a hold-over circuit for feeding back a feedback signal being either a count signal corresponding to a frequency division signal or a count signal corresponding to a hold signal to a phase comparator circuit to the PLL circuit. CONSTITUTION:The PLL circuit is provided with a phase comparator 1, a low pass filter 2 and a VCO 3 the same as those of a conventional PLL circuit and also a hold-over circuit 5 selecting by switchover either an error signal (c) or a hold signal (f) being an error signal (c) in the normal state to be latched corresponding respectively to the normal state or the intermitted state of an input signal (a), giving the selected signal to the low pass filter 2 as a signal Q and feeding back either an output signal B of a counter 6 or a count signal (g) of a counter 55 corresponding to the hold signal (f) to the phase comparation circuit as a feedback signal (b). Then the hold signal (f) being the error signal (c) just before the interruption of the input signal is generated and used to control the VCO 3. |
