发明名称 DEVICE AND METHOD FOR ARITHMETIC PROCESSING
摘要 PURPOSE:To reduce the number of steps in a program concerning the arithmetic processing of data expressed by a short bit length by providing plural computing elements for dividing data into (n) pieces and simultaneously and parallelly executing arithmetic for each of divided data and by providing a result storage means at an arithmetic processor so as to store the arithmetic result. CONSTITUTION:Concerning a computing element 104, the data of an arithmetic object are read from the register of a register file 100 and divided into the (n) pieces corresponding to a control signal from a control circuit 107. The computing element 104 is made switchable between the arithmetics with 32 bits, 16 bits and 8 bits corresponding to the signal from the control circuit 107 for each of divided data. In the case of arithmetic of 16 bits, two pieces of data '1' instructions are executed and in the case of arithmetic of 8 bits, the arithmetic of four data is parallelly executed by one instruction. Then, that arithmetic result is stored in a result storage means 105 by an arithmetic processor 108. Thus, the number of steps in the program for arithmetic processing can be reduced, and processing speed can be accelerated.
申请公布号 JPH07262010(A) 申请公布日期 1995.10.13
申请号 JP19940055586 申请日期 1994.03.25
申请人 HITACHI LTD 发明人 MINAMI TOSHIKA;WATABE MITSURU
分类号 G06F9/38;G06F7/00;G06F7/38;G06F7/50;G06F7/505;G06F9/30;G06F9/305;G06F9/34 主分类号 G06F9/38
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