| 摘要 |
An ATM cell switch comprises a plurality of data input/output link controllers connected to external data links, each link controller comprising a leaky bucket processor to monitor and control cell flow rates, the leaky bucket proces-sor comprising timer means for timing the arrival of each ATM cell, and calculating means to calculate the time interval between the reception of two consecutive cells on the same connection, means for storing a predetermined regular bucket increment, means for determining from the calculated time interval and from the predetermined regular bucket increment the resultant level in the bucket, and means for comparing the resultant level in the bucket with a predetermined maximum level and, if the maximum level will be exceeded, for discarding, or changing the Cell Loss Priority of, the current cell, characterised in that the leaky bucket processor comprises means for performing the calculation of the resultant bucket level for a pair of buckets simultaneously.
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