ON-DELAY CIRCUIT.

摘要

An on-delay circuit using a fail-safe electronic circuit. An input signal higher than a power source potential is inputted to a PUT oscillation circuit. A pulse signal generated with a predetermined time constant is once converted to a level within the range of the power source potential by a level conversion circuit. This signal is inverted and differentiated at its leading edge. The input signal of the PUT oscillation circuit is applied to one input terminal of a fail-safe two-input window comparator and the differential signal is inputted to the other input terminal for self-retention. An output of a logic value 1 is generated from the window comparator with a predetermined delay time. Accordingly, there is provided a fail-safe on-delay circuit the delay time of which is not reduced due to breakdown of a circuit constituent element.