发明名称 A METHOD FOR REDUCING THE SPACING BETWEEN THE HORIZONTALLY-ADJACENT FLOATING GATES OF A FLASH EPROM ARRAY
摘要 The spacing between the horizontally-adjacent floating gates of a "T-shaped" flash electrically programmable read-only-memory (EPROM) array is reduced beyond that which can be photolithographically obtained with a given process by covering the layer of polysilicon that forms the floating gates with two sacrificial layers, exposing strips of the polysilicon layer with a standard photolithographic process, forming spacers that protect a portion of the exposed polysilicon layer, and then etching the layer of polysilicon that remains exposed.
申请公布号 WO9522837(A1) 申请公布日期 1995.08.24
申请号 WO1994US11589 申请日期 1994.10.12
申请人 NATIONAL SEMICONDUCTOR CORPORATION 发明人 BERGEMONT, ALBERT
分类号 H01L21/8247;H01L27/115;(IPC1-7):H01L21/82 主分类号 H01L21/8247
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