| 摘要 |
PURPOSE:To provide a semiconductor diagnostic circuit by which a circuit to be tested can be diagnosed at high frequency clock. CONSTITUTION:A semiconductor diagnostic circuit is provided with a PLL(phase lock loop) circuit 11 to generate high frequency clocks, an ordering resistor 13 to send orders synchronously with the clocks, a circuit 16 to be tested which carries out the orders and sends the results synchronously with the clocks, and a data compressing apparatus 17 to receive and compress the results sent out of the circuit to be tested 16 synchronously with the clocks and to send the compressed results. The circuit is also provided with an AND gate 12 to control the supply of the clocks to the circuit 16 to be tested and the data compressing apparatus 17. |
