发明名称 CIRCUIT AND METHOD FOR EXECUTION OF PARALLEL ADDITION AND AVERAGE OPERATION
摘要 PURPOSE: To provide an adder which is operated with high efficiency when performing many types of addition with words smaller than the width of the adder and can generate the average of two numerals in a single machine cycle. CONSTITUTION: Each operand can be divided into plural subwords. Assure that each operand is to be divided into partial operands just once. In such a case, first (k) bits X0 -Xk-1 of an operand X are the respective bits of 1st partial operand 18 of the word X, and remaining bits Xk -XN-1 are the respective bits of 2nd partial operand 17 of the word X. Similarly, an operand Y is divided into partial words 19 and 20. Here, bits Z0 -Zk-1 are the bits of sum of the partial operands 18 and 20, and bits Zk -ZN-1 are the bits of sum of the partial operands 17 and 19. These two results are called partial sum or subword sum and can be used for calculating the respective average values of two partial operands.
申请公布号 JPH07210369(A) 申请公布日期 1995.08.11
申请号 JP19940294231 申请日期 1994.11.29
申请人 HEWLETT PACKARD CO <HP> 发明人 RUBII BEIIROO RII;JIYON POORU BETSUKU
分类号 G06F7/50;G06F7/505;G06F7/506;G06F7/544;G06F7/575;G06F9/38 主分类号 G06F7/50
代理机构 代理人
主权项
地址
您可能感兴趣的专利