发明名称 Flip-flop circuits for testing LSI gate arrays
摘要 A flip-flop circuit comprising serially connected flip-flops is associated with a combination circuit and configures a scanning circuit for performing a scanning operation in order to test the combination circuit in a test mode. In performing the scanning operation, the flip-flop circuit is preset or cleared and the preset or cleared data is scanned out through the scanning circuit so that the failure of an asynchronous system input circuit connected to a preset or clear terminal of the flip-flop circuit is detected.
申请公布号 US5440569(A) 申请公布日期 1995.08.08
申请号 US19940195606 申请日期 1994.02.14
申请人 FUJITSU LIMITED 发明人 NAITO, MITSUGU
分类号 G01R31/3185;G06F11/267;H03K3/037;(IPC1-7):H04B17/00 主分类号 G01R31/3185
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