| 摘要 |
PURPOSE:To provide the high-speed floating point adder/subtracter for dealing with plural kinds of floating point data formats. CONSTITUTION:Concerning floating point adder/subtracter, a digit matching shift amount calculating part due to exponent subtraction as the first step of floating point adding/subtracting processing is composed of a (y) bit exponent subtracter 102, AND gate 107 for inputting the digit borrow signal of the (y) bit exponent subtracter 102 and a format select signal, (x) bit exponent subtracter 101 for defining the output of the AND gate 107 as a digit borrow input to a least significant digit, and right shifter 103 for inputting data, which link the output of an (x) bit length from the (x) bit exponent subtracter 101 and the output of a (y) bit length from the (y) bit exponent subtracter 102, and being controlled by the format select signal. Since the control of the right shifter 103 can be performed parallelly with exponent subtraction, right shifter control time does not become the controlled speed part of entire processing, and high- speed processing can be provided. |
