发明名称 INPUT INTERRUPT DETECTION CIRCUIT, COMMUNICATION EQUIPMENT AND INPUT INTERRUPT DETECTION METHOD
摘要 PURPOSE:To stably attain input interruption with high reliability regardless of small scale configuration by monitoring logical combination of prescribed multi-bit digital demodulation signals so as to detect input interruption in a multi-value processing QAM communication equipment. CONSTITUTION:A sent multi-value processing QAM signal is demodulated into a multi-bit digital demodulation signal having a most significant bit D1 indicating a sign and a bit D2 representing an amplitude and succeeding to the bit Di. The combination of logical values of the bits D1, D2 of the demodulation signal is monitored for a predetermined period by an exclusive logic arithmetic circuit 1 to be used for detecting input interruption and a discrimination circuit 2 raises an alarm. The circuit detects input interruption stably with high reliability through small scale configuration integrated in a digital demodulation circuit capable of being LSI-integrated independently of an analog level of an input signal without mis-discrimination of input interruption regardless of reception of erroneous data resulting from discrimination of presence of input even when OR result is lost at once.
申请公布号 JPH07193612(A) 申请公布日期 1995.07.28
申请号 JP19930333894 申请日期 1993.12.27
申请人 FUJITSU LTD;NIPPON TELEGR & TELEPH CORP <NTT> 发明人 IWAMATSU TAKANORI;AIKAWA SATOSHI;AKINAGA KOSHIRO
分类号 H04L27/00;H04L27/38 主分类号 H04L27/00
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