| 摘要 |
A hardware arrangement for a fast Fourier Transform includes, an arithmetic unit for executing said fast Fourier Transform, a data memory for storing data to be executed and storing results thereof, and an address generator for generating addresses to be applied to said data memory. The hardware arrangement further is provided with a bit rotation circuit coupled to receive each of said addresses. The circuit rotates a predetermined number of lower bits of each of said addresses such as to locate the least significant bit at the upper bit position of said predetermined number of lower bits and shift the remaining bits towards the least significant bit by one.
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