发明名称 Method for manufacturing semiconductor device with reduced junction capacitance
摘要 A method for manufacturing a semiconductor device in which an opening is formed in an insulation film laid on a semiconductor substrate, and in which an annular trench that is narrower than a minimum width obtained by lithography is formed in the semiconductor substrate along the opening in a self-aligned manner. The method includes the steps of: forming a first insulation film on a main surface of a semiconductor substrate; forming an opening in the first insulation film; forming an annular film along the inner sidewall of the opening; forming a second insulation film on the surface of the semiconductor substrate surrounded by the annular film; removing the annular film to cause the semiconductor substrate to be annularly exposed; forming an annular trench by etching the exposed area of the semiconductor substrate; and forming a film layer containing at least a third insulation film over the entire main surface of the semiconductor substrate including the inside of the annular trench.
申请公布号 US5426067(A) 申请公布日期 1995.06.20
申请号 US19940291998 申请日期 1994.08.18
申请人 NEC CORPORATION 发明人 OGAWA, CHIHIRO
分类号 H01L21/76;H01L21/331;H01L21/822;H01L27/04;H01L29/73;H01L29/732;(IPC1-7):H01L21/76 主分类号 H01L21/76
代理机构 代理人
主权项
地址