发明名称 |
Parallel shift and add circuit and method. |
摘要 |
An apparatus for combining the contents of an X register, shifted by m places, with the contents of a Y register to generate a result Z. The functional unit can also be configured to perform parallel operations on sub-operands in the X and Y registers. The division of the apparatus into sub-operands is controlled by a mask which specifies the boundary of the sub-operands. The shifting operation is accomplished by multiplexers that connect the pth bit of the X register to the adder stage that operates on bit Yp-m of the Y register. Circuitry is provided at the boundary of the sub-operands to prevent the bit signals corresponding to the X register from being routed across a sub-operand boundary. Similarly, circuitry is provided for preventing the carry output of an adder stage that operates on one sub-operand from being propagated to an adder stage that operates on another sub-operand. |
申请公布号 |
EP0655677(A1) |
申请公布日期 |
1995.05.31 |
申请号 |
EP19940112052 |
申请日期 |
1994.08.02 |
申请人 |
HEWLETT-PACKARD COMPANY |
发明人 |
LEE, RUBY BEI-LOH;LAMB, JOEL DAVID |
分类号 |
G06F7/50;G06F7/508;G06F7/52;G06F7/53;G06F7/57;G06F7/575;G06F9/302 |
主分类号 |
G06F7/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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