| 摘要 |
The application is for telecommunication networks of asynchronous transfer mode. The device contains a time stamp generator (TSG) for assigning a time stamp to each cell; a buffer memory (BM); an address memory (FSAM) for memorizing the address of the first sub-cell of each cell; a link memory (LM); and a circuit for indicating the address of the buffer memory that contains the first sub-cell of a cell. This circuit contains in particular: a memory that is accessible by its content, for memorizing a cell identifier (TSTP-OA; TSTP-OM) when a cell is made to wait, where each identifier indicates a time period during which the waiting delay expires, and at least one output from which the cell must be emitted; and a marker memory for each output, where a marker is recorded as soon as a cell is made to wait, to locate the time period during which the waiting delay of this cell will expire; the markers are read starting with the oldest, and only those that correspond to expired delays are validated when the output in question indicates that it is available; and each marker is potentially common to several cells.
|
