| 摘要 |
<p>PURPOSE:To reduce the power consumption by extending the phase of less power consumption in the power down mode where the operation frequency is reduced. CONSTITUTION:The reference clock having a frequency (f) is inputted from a clock signal input terminal 101 to generate a signal CK1A having a frequency f/2 and a signal CK2A, whose phase is delayed by a half period, by a 1/2 frequency divider 203. The signal which is obtained from the signal CK1A by a 1/2 frequency divider 204 and has 174 frequency of CK and the signal CK1A are connected to an AND circuit 207 to output a signal CK1B. A signal having 1/8 frequency of CK and a signal CK2B are connected to an AND circuit 208 to generate a signal CK1C. A power down mode set terminal 102 is set to select the signal CK1A or CK1C by a selector circuit 210, and the selected signal is sent to a non-overlap clock driver 250, and signals K1 and K2 are outputted to a clock signal output terminal 231 and an output terminal 241 respectively.</p> |
