| 摘要 |
In order to employ an output register having a finite number of stages in an arithmetic encoder, it is necessary to provide carryover control, otherwise a register having an impractically large number of stages would be required, i.e., a so-called "infinite" register. The so-called "infinite" output register is emulated by employing a counter and a finite register. To this end, a count is accumulated of sets, i.e., bytes, of consecutive prescribed logical signals of a first kind, i.e., logical 1's, being generated by an arithmetic coding register and possibly modified by a carry indication. The accumulated count is then employed to supply as an output a likenumber of sets including logical signals of a second kind, i.e., logical 0's, or logical signals of the first kind, i.e., logical 1's, depending on whether or not a carry would propagate through the stages of the so-called "infinite" register being emulated.
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