发明名称 |
Scrambling apparatus and descrambling apparatus. |
摘要 |
<p>A scrambling apparatus has at least one of following processing units: a signal inserting processor (2, 3, 4) for inserting a dummy pattern indicating the quantization width in the compressed video data; a conversion processor (50, 5) for scrambling a signal specifying whether field or frame processing is used; a DCT coefficient conversion processor (48, 7, 6) for scrambling a part of the code defining the DCT coefficient; an intra_dc_precision conversion processor (47, 5) for scrambling the intra_dc_precision signal; and an alternate_scan conversion processor (49, 5) for scrambling the alternate_scan signal. A descrambling apparatus reverses the conversion process on the video data scrambled by the scrambling apparatus to restore the video data to the original unscrambled state. <IMAGE></p> |
申请公布号 |
EP0648055(A1) |
申请公布日期 |
1995.04.12 |
申请号 |
EP19940115939 |
申请日期 |
1994.10.10 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
KATTA, NOBORU;MURAKAMI, HIROKI;IBARAKI, SUSUMU;NAKAMURA, SEIJI |
分类号 |
H04N7/167;(IPC1-7):H04N7/167 |
主分类号 |
H04N7/167 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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