| 摘要 |
A statically operated dynamic CMOS logic gate that includes an FET logic network (61) for performing a predefined logic function with respect to its logic inputs, an output node (67), a precharge transistor (63), and in some embodiments an evaluate transistor (64). During operation, the precharge transistor (63) is first turned on by a clock signal during a precharge phase to precharge an output node (67) of the dynamic logic gate (61) to a first voltage state. During the precharge phase, the evaluate transistor (64) is turned off by the clock signal. An evaluate phase typically follows the precharge phase, and during the evaluation phase, the evaluate transistor (64) is turned on by the control signal to allow the logic network (61) to perform the predefined logic function with respect to its inputs, and the logic network (61) selectively charges or discharges the output node (67) to a second voltage state via the evaluate transistor (64) in accordance with the predefined logic function given to the logic inputs to the logic gate. A driver circuit (62) is provided for applying a bias voltage to the gate of the precharge transistor (63) when the precharge transistor (63) is not precharging the output node (67) (e.g. the evaluate phase). The bias voltage has a voltage level that differs from the first voltage state by less than the magnitude of the threshold voltage of the precharge transistor in order for the precharge transistor (63) to operate in a subthreshold conduction region so as to ensure the logic gate's output node (67) to be at the first voltage state when the logic network (61) does not discharge the output node to the second voltage state through the evaluate transistor (64) as a result of the predetermined logic function. In this way, the dynamic logic gate circuit (61) can operate statically with substantially minimized power consumption. |
