| 摘要 |
<p>PURPOSE:To reduce the clock skew between plural internal clock signals and to synchronize the phase of an internal clock signal and that of an external clock signal with each other. CONSTITUTION:An internal clock signal generating circuit 1 generates plural internal clock signals CLK1, CLK2, and CLK3 different in phase based on an external clock signal CLK. The internal clock signal CLK2 synchronized with the external clock signal by a PLL circuit. Internal clock signals CLK1, CLK2, and CLK3 are supplied to internal circuit blocks 21, 22, and 23 respectively. Since generated internal clock signals are different by phases, phases of internal clock signals reaching the internal circuit blocks can coincide with one another even if signal delays are different from one another between the internal clock signal generating circuit 1 and internal circuit blocks 21, 22, and 23.</p> |
