| 摘要 |
<p>PURPOSE: To provide an arrangement structure of an array decoder which can efficiently by laid out, suitable for a high integration and can further suppress a load capacity of a signal line in a multiport memory having RAM array and SAM array. CONSTITUTION: Four sub-cell arrays 10 are arranged in a square formation and pre-decoders 4 and 8 are also arranged in the square, and further, on the side of the pre-decoder of each sub-array 10, a column decoder 100 for a RAM- SAM is arranged, which is formed as a decoder group by grouping the array decoder for RAM and the array decoder for SAM. Therefore, since the array decoders can share one power source line and all the pre-decoders and decoders are connected with each other in the shortest distance, the layout is efficient and suitable for a high integration, and further it becomes possible to suppress a load capacity by shortening all the signal lines with respect to column decoding.</p> |
