| 摘要 |
PURPOSE: To provide a semiconductor integrated circuit device where a flattening treatment and a self-alignment technique are harmonized, and its manufacturing method. CONSTITUTION: In a semiconductor integrated circuit device where a self-aligned transistor in that a region near the transistor is locally flattened is formed, gate electrodes 14a and 14b, silicon nitrides 16a and 16b, and sidewall spacers 18a and 18b are formed, an active region is formed by self-alignment, and an oxide layer 20 is formed and then a glass layer 24 that is melted and coagulated (reflow) is formed on it. Then, the glass layer 24 is etched back, an integrated circuit structure is flattened, the remaining part of a glass layer 24a and the oxide layer 20 located below it are eliminated from only an embedded contact region, a short-circuiting between local mutual connection parts is prevented, a continuity at a mutual connection part on a flat surface is improved, and a region for configuring a chip is reduced.
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