| 摘要 |
The invention discloses a PLL formed by a phase detector, a filter, three VCO's (VCO1, VCO2, and VCO3), a multiplexer, and a frequency divider. The VCO1, VCO2, and VCO3 have different mean frequencies, each oscillating at a frequency controlled according to the voltage value of a phase control signal from the filter. The multiplexer selects one of the VCO's which operate in parallel. If a pulse of a digital phase difference signal UP indicating that an internal signal is delayed in phase with respect to a reference signal is output twice in succession, or if a pulse of a digital phase difference signal DOWN indicating that an internal signal is advanced in phase with respect to a reference signal is output twice in succession, a counter makes the multiplexer change its current VCO selection via a shift register. Accordingly, high-speed PLL pulling is achievable even if a PLL frequency variable-range is expanded.
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